Senior Engineer, Design Verification

Analog Devices

Producción de semiconductores

Valencia, Comunidad Valenciana - Spanien

Project Manager Sénior / Especialista sénior

Experteer Overview

As part of Analog Devices’ CSS group in Valencia, you will contribute to the verification of complex ASIC designs and sub-systems. You’ll shape verification methodologies, architect testbenches, and mentor junior engineers to ensure robust chip-level and block-level verification. You’ll collaborate across analog, firmware, and design teams to enable successful post-silicon validation. This role offers impact in a high-tech, globally focused environment.

Responsabilidades

Verify complex designs and sub-systems using modern verification methodologies
Influence and define verification methodologies adopted by the team
Mentor and guide junior verification engineers in SoC verification
Architect testbenches and develop in UVM or formal verification approaches
Integrate block testbenches into chip-level UVM environment and verify integration
Define test plans and verification strategies for block and chip-level verification
Collaborate with design and firmware teams for test-plan generation and coverage closure
Support post-silicon verification activities with design, evaluation, and applications teams
Engage with analog co-sim and firmware teams to enable top-level verification