Senior Design Verification Engineer

Analog Devices

Producción de semiconductores

Valencia, Comunidad Valenciana - Spanien

Project Manager Sénior / Especialista sénior

Experteer Overview

As a Senior Design Verification Engineer at ADI, you will define and drive verification strategy for the ADG BU in Valencia, applying SystemVerilog and UVM to build reusable verification components. You will work across block, subsystem, and full-chip levels to create plans, develop tests, and measure progress with coverage metrics. You will explore new verification methodologies to handle complex designs and collaborate with global teams to integrate IP/VIP. This role offers the opportunity to shape verification flows that accelerate delivery for intelligent edge applications while contributing to a highly skilled, cross-functional team.

Responsabilidades

Plan, develop, document, and execute verification plans across multiple platforms (simulation and emulation).
Build and enhance SystemVerilog UVM-based environments and verification flows.
Develop, simulate, and debug constrained-random and directed tests aligned with verification plans.
Define functional coverage models, assertions, and metrics to track progress and closure.
Lead verification reviews, analyze coverage, and close gaps to ensure completeness.
Evaluate and unify verification methodologies to improve productivity and efficiency.
Collaborate with global teams to integrate internal and third-party IP/VIP into the verification environment.
Partner with design, architecture, software, and implementation teams to ensure robust design quality and timely delivery.

Requisitos principales

Master’s degree in Computer/Electrical engineering or related field with strong background in digital design and verification.
Experience with object-oriented programming, SystemVerilog/UVM, Python, Perl.
Experience with Cadence, Synopsys, or Mentor tools for simulation.
Experience with MATLAB or SystemC (system and digital modeling languages).
Exposure to design/verification tape-out cycle desirable.
Experience with multi-site teams and 3rd party VIP valuable.

collaborative problem-solving strong communication SystemVerilog UVM constrained-random testing

Descripción del puesto

As a Senior Design Verification Engineer at ADI, you will define and drive verification strategy for the ADG BU in Valencia, applying System…

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