Mixed-Signal Design & Verification Engineer Lead

Monolithic Power Systems

Producción de semiconductores

Barcelona, Cataluña - Spanien

Project Manager Sénior / Especialista sénior

Experteer Overview

In this role you will lead the Mixed-Signal Design team and shape the design/verification framework for complex mixed-signal ICs. You will collaborate with analog, digital, layout, and verification engineers to drive architecture decisions and deliver robust IP. You’ll oversee multiple projects, mentor staff, and contribute to post-silicon validation. The position centers on power management and mixed-signal devices across diverse markets, enabling impactful, cross-functional collaboration. This is a chance to lead technical excellence in a fast-growing semiconductor company.

Responsabilidades

Lead, supervise, and mentor the Mixed-Signal Design Team
Manage multiple projects to meet quality metrics and schedules
Participate in recruitment for the Mixed-Signal group
Analog and Mixed-Signal design, verification, and validation across projects
Define and document analog-digital interfaces and behavioral models
Develop Analog and Mixed-Signal IP, integration, and verification
Layout design involvement
Simulate and debug analog/mixed-signal circuits
Support timing, IO, and DFT constraints for Digital Design
Provide post-silicon validation and characterization support
Collaborate with Analog/Digital/Verification/Physical design teams

Requisitos principales

BSEE with 12 years of ASIC Mixed-Signal design experience or MSEE with 8 years
Ability to work independently and across teams
Proven leadership to manage multiple projects and a small team
Solid knowledge of ASIC development and silicon fabrication processes
Strong background in transistor-level and analog/mixed-circuit design
Understanding of device mismatches, noise, and analog effects
Layout design experience and best-practice knowledge
Experience with simulation tools (Spectre, HSPICE, MATLAB)
Cadence ADE-L and ADE-XL proficiency
Experience with Monte-Carlo, noise, and stability simulations
DRC/LVS experience with Calibre, ICV, etc.
Verilog-AMS for mixed-mode simulations
Verilog, SystemVerilog, Verilog-A for behavioral modelling
DFT techniques (SCAN, LBIST, ABIST, IDDQ)
STA and Mixed-Signal timing/IO constraints for Syn and P&R
Excellent written/verbal communication and teamwork
Nice-to-have: Automotive/ASIL knowledge, power management domain, I2C/I3C/SPI/USB/PMBUS
GitLab and Cliosoft SOS familiarity